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bd91411gw product structure silicon monolithic integrated circuit this product is not designed prot ection against radioactive rays . 1/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 tsz22111 ? 14 ? 001 www.rohm.com datashee t built-in ovp micro usb switch with usb2.0, mhl tm and audio bd91411gw general description bd91411gw is usb connector interface ic. it is possible to use it for the application for the mobile device such as smart phones and mobile phones. features complete solution for mi ni/micro usb connect multiplexing. mhl/usb/uart 2paths, audio 1path, monaural microphone 1path in 4 to 1 multiplexer. compatible with usb high speed/full speed. cecbus to id bypass switch. audio switch handle with negative voltage signal. microphone signal paths to vbus or hdpr are built in. id resistance support to cea936a, battery charging specification (bcs) ver1.2, mcpc, usb-otg and mhl specification. power-on reset. usb charger detection support with bcs ver1.2 specification. over voltage protection (ovp) up to 28v about vb(vbus) input and vc(cradle) input. power multiplexer ovp input about vb and vc. internal low ron fet about ovp(vb and vc). otg power path switch (o utput side in this power path support 28v protection) is built in. vbus linked ldo 4.9v or 3.3v are selectable. i 2 c compatible interface. key specifications ovp switch on resistance: 120m (typ.) over current protection(ocp): 2.0a(min.) regulator output voltage: 3.3v or 4.9v mhl/usb switch on resistance: 5 (typ.) mhl/usb switch on capacitance: 6pf(typ.) vbat standby current: 6a (typ.) operating temperature range: -30 to +85 applications mobile-phones ? smart-phones tablet-pc digital still camera dsc package w(typ.) x d(typ.) x h(max.) ucsp75m3 3.00mm x 3.00mm x 0.85mm typical application circuit hdm1 earl vbdet vcdet vc micout hdp1 earr hdpr hdml vbat id gnd chg_det vddio scl sda rst intb vccin cap_vc cap_vb idsel cbus hdm2 hdp2 otg_det ldosel dss otg_vin usbdisen fact_det vb vout dcdmode vbus d- d+ id gnd usb receptacle cvccin + to charger cradle ccapvc ccapvb to charger internal power for otg to mic amplifier from hp amplifier internal power for system io from hp amplifier to mhl tx/usb trx to usb phy from mhl tx- to usb phy from mhl tx- to host to host to host to host from system reset battery vbreg to usb transceiver cvbref to host to host to host to host rpu fig.1 typical application circuit ucsp75m3
datasheet d a t a s h e e t 2/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw contents 1.pin confi guratio n ............................................................................................................ .............................................................3 2.pin descr iption.............................................................................................................. ...............................................................3 3.block diagram ................................................................................................................ .............................................................4 4.absolute maxi mum rati ngs ..................................................................................................... ....................................................5 5.recommended oper ating ra tings................................................................................................ ...............................................5 6.electrical ch aracteri stic .................................................................................................... ...........................................................6 7. feat ures.................................................................................................................... ................................................................10 7-1.pull down resistance detection in id pin................................................................................... ...........................................10 7-1-1. priorty of mh lsw and id det ection....................................................................................... ......................................10 7-1-2. application with send/end switch .detec tion.............................................................................. ................................10 7-1-2-1. otg applic ation dete ction ............................................................................................. ......................................10 7-1-2-2. mhl applic ation dete ction............................................................................................. .......................................10 7-1-3. enable for id pin pu ll down resistan ce detec tion. ....................................................................... .................................10 7-1-4. retry of id detection sequenc e. ......................................................................................... .........................................10 7-1-5. polling mode of id detection sequenc e. .................................................................................. ....................................10 7-1-6. remove id pin pull down re sistance. (applicat ion detach ment)............................................................ ......................10 7-2. usb port detecti on. ....................................................................................................... .....................................................10 7-2-1. data cont act dete ct/dcd ................................................................................................. ..........................................10 7-2-2. confi guration of dc d time out........................................................................................... ..........................................10 7-2-3. primar y detect ion....................................................................................................... .................................................10 7-2-4. secondar y detection ..................................................................................................... ..............................................10 7-2-5. shortening of second detect ion by enumeratio n prepar ation ............................................................... ....................... 11 7-2-6. sequence retrying....................................................................................................... ............................................... 11 7-2-7. deactivation of usb por tdetection by extarnal pi n and internal register. ............................................... .................. 11 7-3. signal paths .............................................................................................................. ......................................................... 11 7-3-1. hdpr/hdml signal paths .................................................................................................. ........................................ 11 7-3-2. configur ation of muxsw initia l path by dss pi n. ......................................................................... ............................. 11 7-3-3. pull-down resist ance in earr/ rarl pin. .................................................................................. ................................. 11 7-3-4. signal path betwe en id pin and cbus pin. ................................................................................ ................................. 11 7-4. interrupt repor t with in tb pin. ........................................................................................... ................................................. 11 7-4-1. active level selector of intb........................................................................................... ............................................. 11 7-4-2. interr upt polar ity...................................................................................................... ..................................................... 11 7-5. detection of cradle and vbus by vbde t pin and vc det pi n................................................................... ....................... 11 7-6. detection of cradle and vbus by i2c interface readin g..................................................................... ............................... 11 7-7. detection of over current state by i2c inte rface r eading. ................................................................. ................................. 11 7-8. thermal shut do wn. ........................................................................................................ ................................................... 11 7-9. vbreg regulat or. .......................................................................................................... ................................................... 11 7-10. otg m ode cont rol......................................................................................................... ...................................................12 7-11. vbus sig nal path. ........................................................................................................ ....................................................12 7-12. reset syetems ............................................................................................................ .....................................................12 7-12-1. power- on re set......................................................................................................... ...............................................12 7-12-2. hardware reset with rst. ............................................................................................... .........................................12 7-12-3. software reset from i2c interfac e writ ing. ............................................................................. ....................................12 7-13. i 2 c interface electrical characte ristics. ........................................................................................ .....................................12 7-14. i 2 c bus inte rface ................................................................................................................ ..............................................13 7-14-1. start and st op condi tions .............................................................................................. .....................................13 7-14-2. modifi ynig data........................................................................................................ ..................................................13 7-14-3. ackn owledge ............................................................................................................ .................................................14 7-14-4. device addr ess ......................................................................................................... ................................................14 7-14-5. writ e oper aton......................................................................................................... ..................................................15 7-14-6. address roll back specif icati on. ....................................................................................... ..........................................15 7-14-7. read ba ck operat ion. ................................................................................................... .............................................15 8.typical perfo rmance cu rves................................................................................................... ...................................................16 9.application ci rcuit dia gram.................................................................................................. ......................................................17 10.i/o equivalenc e circ uits.................................................................................................... ........................................................18 11.operationa l note s ........................................................................................................... .........................................................22 12.ordering in formati on ........................................................................................................ ........................................................23 13.physical dimension t ape and reel in formation................................................................................ .......................................23 14.marking diagram ............................................................................................................. ........................................................23 15.revision history............................................................................................................ ...........................................................24
datasheet d a t a s h e e t 3/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 1.pin configuration g tmode1 hdm1 hdp1 earl earr id tmode0 f hdml hdm2 hdp2 fact_det cbus vccin vddio e hdpr micout dss rst scl sda vbat d gnd ldosel chg_det usbdisen dcdmode intb gnd c vbreg otg_det (index) vbdet vcdet idsel vc b otg_vin vb cap_vb vout vout vc vc a atest0 vb vb vout vout cap_vc atest1 1 2 3 4 5 6 7 2.pin description no. ball no. ball name i/o function pull down pins configuration when not in use 1 b6,b7,c7 vc i power supply about cradle input open or gnd 2 a2,a3,b2 vb i power supply about usb vbus input open or gnd 3 e7 vbat i power supply about battery voltage open or gnd 4 f7 vddio i power supply for i2c i/f open or gnd 5 f6 vccin o power supply for internal circuit open 6 d1,d7 gnd gnd gnd gnd 7 a4,a5,b4,b5 vout o ovp output open 8 b1 otg_vin i otg power input open or gnd 9 e3 dss i muxsw initial value select signal. gnd 10 a6 cap_vc o cap connect pin for sw1 ovp open 11 b3 cap_vb o cap connect pin for sw2 ovp open 12 c5 vcdet o vc detecting (uvlo < vc < ovlo ) open 13 c4 vbdet o vb detecting (uvlo < vb < ovlo ) open 14 c2 otg_det o otg mode detection open 15 f4 fact_det o factory mode detection open 16 f5 cbus i/o cbus signal path open 17 c1 vbreg o regulator with vbus output open 18 d2 ldosel i regulator output voltage select. gnd 19 e2 micout o mic signal output. open 20 g3 hdp1 i/o mhl/usb/uart d+ signal path1 open 21 g2 hdm1 i/o mhl/usb/uart d- signal path1 open 22 f3 hdp2 i/o mhl/usb/uart d+ signal path2 open 23 f2 hdm2 i/o mhl/usb/uart d- signal path2 open 24 g5 earr i headphone right signal path 500 *1 open 25 g4 earl i headphone left signal path 500 *1 open 26 e1 hdpr i/o mhl/usb/uart/earphone/mic signal path open 27 f1 hdml i/o mhl/usb/uart/earphone signal path open 28 d3 chg_det o usb charging port detection open 29 g6 id i/o id pull down resistance connecting pin open 30 e5 scl i i2c clock signal input gnd 31 e6 sda i/o i2c data signal input gnd 32 d6 intb o interrupt signal output open 33 e4 rst i reset signal input gnd 34 d4 usbdisen i usb port detection disable. gnd 35 g7 tmode0 i test pin(for vendor test) 1m open or gnd 36 g1 tmode1 i test pin(for vendor test) 1m open or gnd 37 a1 atest0 i/o test pin(for vendor test) open 38 a7 atest1 i/o test pin(for vendor test) open 39 d5 dcdmode i dcd time out select. gnd 40 c6 idsel i i2c device address select gnd 41 c3 index - index mark open *1 turn on and turn off can be controlled by register. (bottom view) fig.2 pin configuration
datasheet d a t a s h e e t 4/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 3.block diagram hdm1 earl vbdet vout vcdet vc sw1 ilmt vcdet tsd vbdet sw2 ilmt to sw, main control vcsw vbsw micout sw4 micsw sw5 usb port detection muxsw hdp1 earr to main control vb hdpr hdml vc vbat id detection id to main control gnd chg_det vddio scl sda rst intb iddet usbchgdet muxsw micswsw4,5 vc sws w1 sw control vcswsw1 vbswsw2 micswsw4 vccin cap_vc cap_vb idsel vb vbreg cbus hdm2 hdp2 cbus_sw vbreg vb to sw , main control cbus_sw vbreg otg_det ldosel dss otg_vin otgsw usbdisen fact_det vbs wsw2 main control tmode0 tmode1 atest0 atest1 vc vc vb vb gnd vout vout vout dcdmode vout vccin vccin fig.3 block diagram
datasheet d a t a s h e e t 5/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 4.absolute maximum ratings (ta=25 c) item symbol rating unit maximum supply voltage1 (vb, vc) vin1 -0.3 30 v maximum supply voltage2 (vbat) vin2 -0.3 6.0 v maximum supply voltage3 (vddio) vin3 -0.3 4.5 v maximum supply voltage4 (hdp1, hdm1,) vin4 -1.0 7.0 v maximum supply voltage5 (hdp2, hdm2) vin5 -1.0 7.0 v maximum supply voltage6 (eapr, earl) vin6 -1.5 7.0 v maximum supply voltage7 (hdpr, hdml,) vin7 -1.5 7.0 v maximum supply voltage8 (vout, cap_vb, cap_vc, otg_vin) vin8 -0.3 7.0 v maximum supply voltage9 (others pins) vin9 -0.3 6.0 v power dissipation pd 1346 (*1) mw operating temperature range topr -30 +85 storage temperature range tstg -55 +125 *1 this value is the permissible loss using a ro hm specification board (50mm x 58mm board mounting). at the time of pcb mounting the permissible loss varies with the size and material of board. when using more than at ta=25 , it is reduced 10.77 mw per 1 . caution use in excess of this value may result in damage to t he device . moreover, normal operation is not protected. 5.recommended operating ratings (ta=25 c) item symbol range unit vb, vc voltage vb 3.8 28 v vbat voltage vbat 2.9 4.6 v vddio voltage vddio 1.7 3.0 v otg_vin voltage votg 4.40 5.25 v
datasheet d a t a s h e e t 6/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 6.electrical characteristic (unl ess otherwise specified, ta=25 c, vbat=3.6v, vb=5.0v, vc=5.0 v, vddio=1.8v, otg_vin=0v) parameter symbol min. typ. max. unit condition circuit current vbat circuit current 1 (standby) iqvbat1 - 6 20 a vddio circuit current 1 (standby) iqvddio1 - 0.0 1.0 a vbat=3.6v, vddio=1.8v vb=vc=open, otg_vin=0v id=open vbat circuit current 2 (hdsw =on) ) iqvbat2 - 3 10 a vb circuit current 2 (hdsw =on) iqvb2 - 210 450 a vbat=3.6v, vddio=1.8v vb=5v, vc=open, otg_vin=0v id=open hdsw=on vbat circuit current 3 (hpsw,micsw= on) iqvbat3 - 55 150 a vbat=3.6v, vddio=1.8v, vb=vc=open, otg_vin=0v id=287k pull down hpsw,micsw=on vc circuit current 4 (standby) iqvc4 - 150 300 a vc=5.0v, vb=0.0v, otg_vin=0v, vbat circuit current 5 (otgsw =on) iqvbat5 - 3 10 a otg_vin circuit current 5 (otgsw =on) iqotg5 - 230 450 a vbat=3.6v, vddio=1.8v, vb=vc=open otg_vin=5v id=0k pull down otgsw=on electrical characteristic (unl ess otherwise specified, ta=25 c, vbat=3.6v, vb=vc=5.0v, vddio=1.8v, otg_vin=0v) parameter symbol min. typ. max. unit condition digital characteristics(digital pins: scl, sda, rs t, intb, chg_det, otg_det, fact_det ,vcdet and vbdet, idsel, ldosel, usbdisen, dcdmode, dss) input "h" level (scl, sda, rst) vih1 0.8 vddio - vddio+0.3 v input "l" level (scl, sda, rst) vil1 -0.3 - 0.2 vddio v input leak current (scl, sda, rst) iic1 -1 0 1 a pin voltage: vddio output voltage ?l? (sda vols da - - 0.4 v iol=6ma output voltage l (intb, vcdet, vbdet, chg_det, otg_det, fact_det) vol1 - - 0.3 v source=1ma off leakage current (intb, chg_det, otg_det, fact_det) iioff1 -3 - 3 a vin=vddio off leakage current (vcdet, vbdet) iioff2 -3 - 3 a vin=vc(vcdet) or vb(vbdet) input h level (idsel, usbdisen,dcdmode, dss vih2 0.8 vccin - vccin+0.3 v *1 input ?l? level (idsel, usbdisen,dcdmode, dss vil2 -0.3 - 0.2 vccin v *1 input h level (ldosel vih3 2.0 - vccin+0.3 v *1 input l level (ldosel vil3 -0.3 - 0.6 v input leakage current(idsel, ldosel, usbdisen, dcdmode, dss iic2 -1 0 1 a pin voltage: vccin diode forward voltage vf - 0.6 - v *1 vccin = (vout or vbat or vb or vc) ? vf
datasheet d a t a s h e e t 7/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw electrical characteristic ( unless otherwise specified, ta = 2 5 c, vbat=3.6v, vb=5.0v, vc=0.0v, vddio=1.8v, otg_vin=0v) parameter symbol min. ty p. max. unit condition ovp (vb : sw2 ) uvlo release voltage uvlo 1h 3.6 3.8 4.0 v vin=up uvlo detect voltage uvlo1l 3.0 3.125 3.25 v vin=down ovlo detect voltage ov lo1 6.2 6.4 6.6 v vin=up ovlo hysteresis voltage ovloh1 - 120 - mv vin=down over current limit ilm1 2.0 - - a on resistance of sw ron1 - 120 250 m vb C vout sw start up delay time ton1 - 5 10 msec output turn off time toff1 - 1 5 sec reverse leak current ileak1 -3 - 3 a vb=0.0v, vc=5.0v electrical characteristic ( unless otherwise specified, ta = 2 5 c, vbat=3.6v, vb=0.0v, vc=5.0v, vddio=1.8v, otg_vin=0v) parameter symbol min. ty p. max. unit condition ovp (vc : sw1 ) uvlo release voltage uvlo 2h 3.6 3.8 4.0 v vin=up uvlo detect voltage uvlo2l 3.0 3.125 3.25 v vin=down ovlo detect voltage ov lo2 6.2 6.4 6.6 v vin=up ovlo hysteresis voltage ovloh2 - 120 - mv vin=down over current limit ilm2 2.0 - - a on resistance of sw ron2 - 120 250 m vc C vout sw start up delay time ton2 - 5 10 msec output turn off time toff2 - 1 5 sec reverse leak current ileak2 -3 - 3 a vb=5.0v, vc=0.0v electrical characteristic ( unless otherwise specified, ta = 2 5 c, vbat=3.6v, vb=5.0v, vc=0.0v, vddio=1.8v, otg_vin=0v) parameter symbol min. ty p. max. unit condition vbreg output voltage 3.3v mode ldovout 33 3.20 3.30 3.40 v ldosel=h, iload = 1ma output voltage 4.9v mode ldovout 49 4.75 4.90 5.05 v ldosel=l, iload = 1ma output current ldomaxi 30 - - ma electrical characteristic ( unless otherwise specified, ta = 2 5 c, vbat=3.6v , vb=vc=0v, vddio=1.8v, otg_vin=5v) parameter symbol min. ty p. max. unit condition otgsw on resistance of sw ron otgsw - 0.2 0.5 otg_vin=5.0v otgsw=on output turn off time toff3 - 0.2 5 sec
datasheet d a t a s h e e t 8/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw electrical characteristic ( unless otherwise specified, ta = 2 5 c, vbat=3.6v, vddio=1.8v , vb=vc=0v, otg_vin=0v) parameter symbol min. typ. max. unit condition hpsw (earr,earl) analog signal input range vin_lr -1.4 1.4 v on resistance ron hpsw 5 10 earr = earl= 0v sink=10ma total harmonic distortion thd_hp 0.02 0.10 % f=1khz vin=1.4vpp rl=16 filter:20khz lpf cross talk ct -90 db rl=16 , f=1khz filter: din audio pull down resistance rpd hpsw 500 hpsw start up time tuphp - - 2 ms hpsw off->on electrical characteristic ( unless otherwise specified, ta = 2 5 c, vbat=3.6v, vb=5.0v, vddio=1.8v, vc=0v, otg_vin=0v) parameter symbol min. typ. max. unit condition hdsw (hdp1, hdm1, hdp2, hdm2) sw resistance when on ron hdsw 5 10 vin=3.3v or 0v input current when off iioff -3 3 a vin=3.3v or 0v vb=open sw capacitance csw (6) pf hdsw on hdsw start up time tuphd 2 ms hdsw off->on electrical characteristic ( unless otherwise specified, ta = 2 5 c, vbat=3.6v, vddio=1.8v , vb=vc=0v, otg_vin=0v) parameter symbol min. typ. max. unit condition micsw (mic : sw4, sw5 ) analog signal input range vin_mic 0 2.5 v sw resistance when on ron micsw 20 40 vin=2.5v or 0v input current when off iioff -3 3 a vin=2.5v or 0v total harmonic distortion thd_mic 0.02 0.10 % f=1khz vin=1.0vpp vbias=2.0v rl=10k filter:20khz lpf micsw start up time tupmic - - 2 ms micsw off-> on electrical characteristic ( unless otherwise specified, ta = 2 5 c, vbat=3.6v, vddio=1.8v , vb=vc=0v, otg_vin=0v) parameter symbol min. typ. max. unit condition cbussw on resistance of sw ron cbussw 5 10 vin=3.3v or 0v cut off frequency fccbus - (100) - mhz @-3db leak current when off iioff -3 3 a vin=3.3v or 0v cbussw start up time tupcbus - - 2 ms cbussw off->on
datasheet d a t a s h e e t 9/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw electrical characteristic ( unless otherwise specified, ta = 2 5 c, vbat=3.6v, vb=5.0v, vddio=1.8v, vc=0v, otg_vin=0v) parameter symbol min. typ. max. unit condition usbchg_det vdp_src voltage (d+ output voltage) vdp_src 0.5 0.6 0.7 v io=0 200ua vdm_src voltage (d- output voltage) vdm_src 0.5 0.6 0.7 v io=0 200ua rcd resistance (d+ pull up resistance) rcd 75 100 125 k not usb port detect (host d+ pull down resistance) rhdp 100 - - k vdat_ref voltage (d+/d- detect voltage) vdat_ref 0.3 0.35 0.4 v when hdpr/hdml up vlgc voltage (d+/d- detect voltage) vlgc 1.2 1.4 1.6 v when hdpr/hdml up d+ sink current idp_sink 50 85 150 ua v(hdpr) = 0.6v d- sink current idm_sink 50 85 150 ua v(hdml) = 0.6v electrical characteristic ( unless otherwise specified, ta = 2 5 c, vbat=3.6v, vb=5.0v, vddio=1.8v) parameter symbol min. typ. max. unit condition id ridopen 1000 - - k open detection rid1 - 797 - k rid2 - 557 - k rid3 - 440 - k rid4 - 390 - k rid5 - 287 - k rid6 - 200 - k rid7 - 180 - k rid8 - 124 - k rid9 - 102 - k rid10 - 68 - k rid11 - 47 - k rid12 - 36.5 - k rid13 - 1 - k connected resistance detect rid14 - 0 50 gnd detection comph detection voltage ratioh 85 90 95 % ratio = 100 x v (id) / vccin [%] when id voltage is up. compl detection voltage ratiol 22 26 30 % ratio = 100 x v (id) / vccin [%] when id voltage is down
datasheet d a t a s h e e t 10/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 7.features 7-1.pull down resistance detection in id pin. after power-on reset is released by applying a operating voltage to the vb, vc or vbat pin, the idrdet block is turned on and becomes ready for insertion detection by the 1.2-m ? pull-up resistance. insertion will be detected by connecting the pull-down resistance to the id pin. insertion will be detected also when an operatin g voltage is applied to the vb, vc or vbat pin with t he pull-down resistance connected to the id pin when ad conversion will be completed, the interrupt will be triggered. 7-1-1.priority of mhlsw and id detection. when the signal path connecting the id pin and the cbus pin is turned on, all functions for detec ting the resistance value of t he id pin are disabled. 7-1-2.application with send/end switch detection. when the detected value of the resistance connected to the id pin is 797 k ? , 557 k ? , 287 k ? , or 47 k ? , the comparator compl for judging presses on the send/end switch will be turned on. by pressing the send/end switch of the application, "1" will be written to the register, and at the same time, an interrupt will be triggered at the intb pin. 7-1-2-1.otg application detection when the detected value of the resistanc e connected to the id pin is below 20 , the otg_det pin will be driven to l assuming that a otg device is detected and ?1? will be written to register. 7-1-2-2.mhl application detection when the detected value of the resist ance connected to the id pin is 1k , a mhl application is detected. 7-1-3.enable for id pin pull down resistance detection. the function of detecting the value of the resistance connected to the id pin is turned on in the initial state but can be turn ed on or off by changing the setting in the register. 7-1-4.retry of id detection sequence. during the period from the detecti on of the value of the id pin pull-down resist ance to detection of removed application, a ret ry can be made to ad-convert the value of the id pin pull-down re sistance at any desired timing by changing the setting in the register. 7-1-5.polling mode of id detection sequence. the lsi will enter polling mode, in which the resistance value of the id pin will be repeatedly detected, an interrupt will tri gger to the intb pin only when both id resistance or register will be updated. 7-1-6.remove id pin pull down resistance. (application detachment) pull-out detection will occur if the pull-down resistance is disconnected from the id pin with the comparator comph turned on. after detection of removed application, and an in terrupt will be triggered at the intb pin. 7-2.usb port detection. when the voltage is normally applied to the vb pin and power-on reset is released, the usb port detection function will be turned on and automatically detect the ci rcuit connected to the hdpr pin and to the hdml pin. the usb port detection function can identify a standard downstream port (sdp), a dedicated charging po rt (dcp), and a charging downstream port (cdp) that are compliant with bcs rev. 1.2. ports, except for some dedicated chargers, are designed to be sdp detected according to bcs rev. 1.2 in pr inciple if they are incompliant with usb standards or bcs. when usb port detection will be completed, the interrupt will be triggered. 7-2-1.data contact detect/dcd in data contact detection, contact detection to usb data pin (d+) is performed via hdpr pin. usb data pin contact is completed or timed out, and then this lsi performs primary detection. 7-2-2.configuration of dcd time out. the timeout period can be selected by the dcdmode external pin. 7-2-3.primary detection in the primary detection, the hdml pin wi ll be compared to identify whether the ty pe of the connection destination host port is a bcs-compliant charging port or the port defined in usb 2.0. 7-2-4. secondary detection in the secondary detection, to identify whether the type of t he connection destination host port is a dedicated charging port compliant with bcs1.2 (bcs-compliant dedicated charger) or a charging downstream port (bcs-complaint charging port through which data can be communicated). whichever type of charging port is detected, the result wi ll be stored in the register, and t he chg_det pin will be driven to inform that a charging port has been connected.
datasheet d a t a s h e e t 11/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 7-2-5.shortening of second detecti on by enumeration preparation the second detection after primary is det ected has already been shortened while judging the usb port when a portable device equipped with this lsi is possible enumeration and cdp will be detected compulsorily. 7-2-6.sequence retrying. after the completion of the usb port detection (sdpdet, cdpde t, or dcpdet in the state tr ansition diagram), detection can be retried at any timing. retries will not be accepted while usb port detection is operating. 7-2-7.deactivation of usb port detection by external pin and internal register. the combination of the usbdisen external pin and the usbdet ctrl@02h register makes it possible to freely turn on or off the usb port detection function. 7-3.signal paths this lsi is capable of controlling the signal paths between the hdpr/hdml pins and the hdp1/hdm1, hdp2/hdm2,earr/earl, and mi cout pins from the i2c interface. it is capa ble of controlling the signal path between the vb pin and the micout pin as well. for mhl transmission/usb transmission, use the path to hd p1/hdm1 or to hdp2/hdm2 enabling high-speed transmission. the signal paths to earr/earl and to micout do not support high-speed signal transmission. 7-3-1.hdpr/hdml signal paths the hdpr pin has a signal path to each of the hdp1, hdp2, earr, and micout pins, whereas the hdml pin has a signal path to each of the hdm1, hdm2, and earl pins. 7-3-2.configuration of muxsw initial path by dss pin. the initially selected state of the signal paths can be controlled by the dss pin. when the state of the dss pin is "l," the si gnal path to the hdp1/hdm1 pin will be selected. when the state of the dss pin is "h," t he signal path to the hdp2/hdm2 pin will be selected. 7-3-3.pull-down resistance in earr/rarl pin. a 500 ? pull-down resistance exists in the signal paths to the earl pin and the earr pin. the on/off state of these resistances can be controlled independently by the register. 7-3-4.signal path between id pin and cbus pin. the id pin has a signal path to the cbus pin. the signal paths can be selected in the register. 7-4.interrupt report with intb pin. this lsi reports such events as the completion of detection of the resistor connected to the id pin and the completion of usb port detection to trigger as interrupt signals to the intb pin. the intb pin is of an nch open drain structure, and the logic o f an interrupt to be triggered is determined by the register. in the initial state, the in tb pin is set to be driven to l when an interrupt is triggered. the output of t he pin is hi-z when there is no interrupt. 7-4-1.active level selector of intb. the active level for interrupts can be selected in the register. in the initial state, the value in the register is "0," which drives the intb pin to "l" at the time of the trigger of an interrupt. by writing "1" into the register, the intb pin will open (hi-z) at the time of the trigger of an interrupt. 7-4-2.interrupt polarity. interrupt polarity can be changed by writing regi ster. in initial state intb is droved with l when interrupt will be triggered. 7-5.detection of cradle and vbus by vbdet pin and vcdet pin. the application of a voltage from the vbus or cradle c an be detected using the vbd et pin or vcdet pin. 7-6.detection of cradle and vbus by i2c interface reading. the application of the voltage to the vbus pin or cradle can be c hecked through the i2c interface by controlling of registers. 7-7.detection of over current st ate by i2c interface reading. this lsi has an independent ocp in each of the vb and vc power supply systems, and its over-current state can be detected by accessing it fr om the i2c interface. 7-8.thermal shut down. if the junction temperature exceeds the set temperature, the thermal shutdown circui t will become activated and turn off the sw1 and sw2 of the ovp. the ts d detection temperature is 180 , and the hysteresis temperature for recovery is 10 . 7-9.vbreg regulator. this lsi has a regulator driven by the vbus voltage. the output from the regulator can be tur ned on by the vbreg pin in the default state by increasing the voltage of the vb pin to uvlo or a higher level. the vbreg output pin is available for external applications, and two output voltage levels can be selected by ldosel pin.
datasheet d a t a s h e e t 12/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 7-10.otg mode control to permit power supply from a portable device in the on-the-go mode of usb2.0, this lsi has an independent power path from the otg_vin pin to the vb pin. 7-11.vbus signal path. this lsi can select the signal path from the vb pin to the micout pin. by setting "1" in the register with uvlo applied to the vb pin, the vb pin and the micout pin wi ll be connected to each other. these pins will be disconnected by setting "0" in the register. 7-12.reset systems this lsi has three reset modes - "power-on re set," "hardware reset," and "software reset." any resets initialize all functions include all registers. 7-12-1.power-on reset power-on reset initializes all of the functi ons of this lsi. when vccin is supplied, power-on reset will be automatically relea sed as the uvlo of the vb, vc, or vbat pin is cleared. 7-12-2.hardware reset with rst. a hardware reset is triggered by external pin rst and can reset all of the functions of this lsi. rst is an h enable pin. it triggers a reset when a voltage within the vih voltage range is applied to the rst pin, and releases the reset when a voltage within the vil voltage range is applied to the rst pin. 7-12-3.software reset from i2c interface writing. a software reset can be executed by writing "1" into register fr om the i2c interface. a software reset can initialize all of th e functions of this lsi. 7-13.i 2 c interface electrical characteristics. ac characteristics on i 2 c bus. characteristics sign min max unit clk clock frequency f clk 0 400 khz clk clock ?low? time t low 1.3 - s clk clock ?high? time t high 0.6 - s bus free time t buf 1.3 - s start condition hold time t hd.sta 0.6 - s start condition setup time t su.sta 0.6 - s data input hold time t hd.dat 0 0.9 s data input setup time t su.dat 100 - ns stop condition setup time t su.sto 0.6 - s clk data (input) t f t high t low t r t su.sto t su.dat t hd.dat t su.sta t hd.sta t buf fig 1. scl/sda bus ac timing
datasheet d a t a s h e e t 13/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw clk data (input) t wr stop condition acknowledge output write data input start condition d o fig 2. scl/sda bus ac timing 7-14.i 2 c bus interface 7-14-1.start and stop conditions when clk is set at "h" and data is changed from "h" and "l ," a start condition will be established, and access will begin. by setting changing sda from "l" to "h " with clk set at "h," a stop condition will be satisfied, and access will be terminated. all commands begin with a start condition and stop with a stop condition. if a stop condition is generated in the middle of reading, reading will be discontinued, and the application will enter standby mode. if a stop condition is generated in the midd le of writing, writing will be suspended until the next start condition, and the application will enter standby mode. t su .sta t hd .sta t su .sto clk data start condition stop condition fig. 3. start and stop condition ac timing. 7-14-2.modifying data one-bit data is transferred while scl is "h". during bit data tr ansfer, the signal transition of sda cannot be executed while c l is "h". when scl is "h" and sda changes, a start condition or stop condition will be generated and interpreted as a control signal. t su .dat t hd .dat clk data modify data modify data fig 4. data transfer ac timing.
datasheet d a t a s h e e t 14/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 7-14-3.acknowledge after a start condition is generated, data will be transferred in eight-bit blocks. after data transfer in eight-bit blocks, th e transmitter opens sda in the ninth cycle, and the receiver return s an acknowledge signal in the ninth cycle by changing sda to "l." the data is thereby received in a proper manner. during writing, the receiver returns an acknowledge signal eac h time it receives eight-bit data, and the transmitter receives the signal. during reading, the transmitter returns an acknowledge signal af ter it receives an address following a start condition. the transmitter then receives read data and opens the bus to wa it for an acknowledge signal from the receiver. when an acknowledge signal is detected, the receiv er outputs the next address data unle ss a stop condition is generated. unless acknowledge signal is detected or stop condition is generated, the receiver does not enter standby mode. the bus is kept open until an acknowledge signal or stop condition is detected. clk data 18 9 data start condition acknowledge output fig 5. acknowledge ac timing. 7-14-4.device address after a start condition is generated, a seven-bit device addr ess and the a one-bit read/write command selection bit will be input. the device address is "1101110" when idsel is "h" (vccin short), or "1101010" when idsel is "l" (gnd short). a one-bit (r/e read/write) signal becomes a read command when it is set at "1," or a write command when it is set at "0."if the device address does not match, the command will not be executed. device address code read/write instruction msb lsb r/w a7 a6 a5 a4 a3 a2 a1 idsel 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 1 i 2 c device address
datasheet d a t a s h e e t 15/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 7-14-5.write operation to write data to the designated address, in put the device address, the one-bit signal of "0" (r/w command selection bit), the word address, and the data to be written after the start condition. the application enters standby mode upon generation of a stop condition. x s x x x x x x 0 a w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0 a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a p device address r/w (write) word address write data (n) write data (n+1) increment register address a = acknowledge (sda low) a = not acknowledge (sda high) increment register address s = start condition p = stop condition d 7 d 0 a fig 6. write protocol sequence. write a start condition, a device address, a one-bit signal of "0" (r/w command selection bit), a word address (n), and address (n) data, and then address (n +1) data. the acknowledge signal will become "0" or be checked unless a stop condition is generated. 7-14-6. address roll back specification. write, read, and complex read will perform, and the word address will be rolled over by address 00h when the address reaches 07h. 7-14-7. read back operation. when reading data from the designated address, the data to be read will be output by writing a device address, a one-bit signal of "0" (r/w command selection bit), and a word address after a start condition and then inputting a start condition, a device address, and a one-bit signal of "1" (r/w command selection bit). the bus opens with a stop condition. x s x x x x x x 1 a device address r/w (read) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data (n+1) a p increment register address a = acknowledge (sda low) a = not acknowledge (sda high ) s = start condition p = stop condition d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data (n) increment register address a d 7 d 0 a fig 7 read back protocol sequence. x s x x x x x x 0 a a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a device address r/w (write) word address x sr x x x x x x 1 a device address r/w (read) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data (n) increment register address a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data (n+ 1) a p increment register address a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition sr = repeated start condition p = stop condition d 7 d 0 a fig 8. complex read back protocol sequence. complex read back a start condition, a device address, a one-bit signal of "0" (r/w command selection bit), a word address (n), and address (n) data, and then address (n +1) data. the a cknowledge signal will become "0" or be checked unless a stop condition is generated.
datasheet d a t a s h e e t 16/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 8.typical performance curves fig12.mhl eye-pattern(720p, 60hz) fig13.mhl eye-pattern(480p, 60hz) fig14.usb eye-pattern(high-speed)
datasheet d a t a s h e e t 17/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 9.application circuit diagram hdm1 earl vbdet vout vcdet vc sw1 ilmt vcdet tsd vbdet sw2 ilmt to sw, main control vcsw vbsw micout sw4 micsw sw5 usb charger detection muxsw hdp1 earr to main control vb hdpr hdml vc vbat id detection id to main control gnd chg_det vddio scl sda rst intb iddet usbchgdet muxsw micswsw4,5 vc sws w1 sw control vcswsw1 vbswsw2 micswsw4 vccin cap_vc cap_vb idsel vb vbreg cbus hdm2 hdp2 cbus_sw vbreg vb to sw , main control cbus_sw vbreg otg_det ldosel dss otg_vin otgsw usbdisen fact_det vbs wsw2 main control tmode0 tmode1 atest0 atest1 vc vc vb vb gnd vout vout vout dcdmode vout vccin vccin vbus d- d+ id gnd receptacle 0.1f + to charger cradle 0.1f 0.1f to charger to host vddio to host vddio to host vddio to usb transceiver internal power for otg to mic amplifier from hp amplifier to host vddio internal power for system io from hp amplifier to mhl tx/usb trx to usb phy from mhl tx+ to usb phy from mhl tx- to host to host to host to host from system reset 1.0f battery fig.15 application circuit diagram
datasheet d a t a s h e e t 18/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 10.i/o equivalence circuits g1 g7 e4 e5 tmode0 tmode1 rst scl ball no. ball name i/o equivalence circuits vccin g1 g7 vddio e4 e5 e3 c6 d2 d4 d5 dss idsel ldosel usbdisen dcdmode vccin e3 c6 c4 c5 vcdet vbdet c4 c5 e6 sda vddio e6 d2 d4 d5
datasheet d a t a s h e e t 19/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw b6 b7 c7 a6 a4 a5 b4 b5 a2 a3 b2 b3 b1 vc vc vc cap_vc vout vout vout vout vb vb vb cap_vb otg_vin ball no. ball name i/o equivalence circuits e2 micout e1 f1 hdpr hdml a3 to mic_sw a2 b2 a5 a4 b4 b7 b6 c7 b5 b3 b1 a6 to vb to hdpr e2 to hdp1 to hdp2 to earr to hdm1 to hdm2 to earl e1 f1 to mic_sw(sw5) sw 5 sw4 sw 3 sw 2 sw1
datasheet d a t a s h e e t 20/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw f6 c1 vccin vbreg ball no. ball name i/o equivalence circuits f6 a7 a1 atest1 atest0 e7 f7 vbat vddio f5 cbus vbat vb c1 vb a7 a1 f7 e7 vc f5 cbussw vout
datasheet d a t a s h e e t 21/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw g2 g3 g4 g5 hdm1 hdp1 earl earr ball no. ball name i/o equivalence circuits g2 d6 f4 d3 c2 intb fact_det chg_det otg_det g6 id f2 f3 hdm2 hdp2 500 hp sw hdsw1 g3 g4 g5 f2 hdsw2 f3 vddio d6 vccin 200k 1.3m + - g6 4k cbussw f4 c2 d3
datasheet d a t a s h e e t 22/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 11.operational notes 1) absolute maximum ratings if applied voltage, operating temperature range (topr), or other absolute maximum ratings are exceeded, there is a risk of damage. since it is not possible to identify short, open, or ot her damage modes, if special modes in which absolute maximum ratings are exceeded are assumed, consider ap plying fuses or other physical safety measures. 2) recommended operating range this is the range within which it is possible to obtai n roughly the expected characteristics. for electrical characteristics, it is thos e that are guaranteed under the conditions for ea ch parameter. even when these are within the recommended operating range, voltage and te mperature characteristics are indicated. 3) reverse connection of power supply connector. there is a risk of damaging the lsi by reverse connection of t he power supply connector. for protection from reverse connection, take measures such as externally placing a diode between the power supply and the power supply pin of the lsi. 4) power supply lines in the design of the board pattern, make powe r supply and gnd line wiring low impedance. when doing so, although the digital power supply and analog po wer supply are the same potential, separate the digital power supply pattern and analog power supply pattern to deter digital noise from entering the analog power supply due to the common impedance of the wiring patterns. similarly take pattern design into acco unt for gnd lines as well. furthermore, for all power supply pins of the lsi, in conjun ction with inserting capacitors between power supply and gnd pins, when using electrolytic capacitors, determine constants upon adequately confirming that capacitance loss occurring at low temperatures is not a problem fo r various characteristics of the capacitors used. 5) gnd voltage about the pins except for earr, earl, dprxr and dmtxl, make the potential of a gnd pin such that it will be the lowest potential even if operating below that. in addition, confirm that there are no pins for which the potential becomes less than a gnd by actually including transition phenomena. 6) shorts between pins and miss assemble when assemble in the set board, pay adequate attention to or ientation and placement discrepancies of the lsi. if it is assembled erroneously, there is a risk of lsi damage. ther e also is a risk of damage if a foreign substance getting between pins or between a pin and a power supply or gnd shorts it. 7) operation in strong magnetic fields be careful when using the lsi in a strong magnetic field, since it may malfunction. 8) inspection in set board when inspecting the lsi in the set board, since there is a risk of stress to t he lsi when capacitors are connected to low impedance lsi pins, be sure to discharge for each process. moreover, when getting it on and off of a jig in the inspection process, always connect it after turning off t he power supply, perform the inspection, and remove it after turning off the power supply. furthermore, as countermeas ures against static electricity, use grounding in the assembly process and take appropriate care in transport and storage. 9) input pins parasitic elements inevitably are formed on a lsi structure due to potential relationships. because parasitic elements operate, they give rise to interference with circuit operati on and may be the cause of malf unctions as well as damage. accordingly, take care not to apply a lower voltage than gnd to an input pin or use the lsi in other ways such that parasitic elements operate. moreover, do not apply a volt age to an input pin when the power supply voltage is not being applied to the lsi. furthermore, when the power supply voltage is being applied, make each input pin a voltage less than the power supply voltage as well as within the guaranteed values of elec trical characteristics. 10) ground wiring pattern when there is a small signal gnd and a large current gnd, it is recommended that you separate the large current gnd pattern and small signal gnd pattern and provide single poi nt grounding at the referenc e point of the set so that voltage variation due to resistance components of the pattern wiring and large currents do not cause the small signal gnd voltage to change. take care that the gnd wiring pattern of externally attached components also does not change. 11) externally attached capacitors when using ceramic capacitors for externally attached ca pacitors, determine constants upon taking into account a lowering of the rated capacitance due to dc bias and capa citance change due to factors such as temperature. 12) thermal shutdown circuit (tsd) when junction temperatures become 180 c (typ) or higher, the thermal shut down circuit operates and turns ovp switch off. the thermal shutdown circuit, which is aim ed at isolating the lsi from thermal runaway as much as possible, is not aimed at the protection or guarantee of the lsi. therefore, do not continu ously use the lsi with this circuit operating or use the lsi assuming its operation. 13) thermal design perform thermal design in which there ar e adequate margins by taking into account the permissible dissipation (pd) in actual states of use. status of this document the japanese version of this document is formal specification. a customer may use this translation version only for a reference to help reading the formal version. if there are any differences in translation version of this document formal version takes priority
datasheet d a t a s h e e t 23/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 12.ordering information b d 9 1 4 1 1 g w - e 2 part number package gw: ucsp75m3 packaging and forming specification e2: embossed tape and reel 13.physical dimension tape and reel information ucsp75m3(bd91411gw) 14.marking diagram ucsp75m3(bd91411gw) top view product name. lot no. ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin
datasheet d a t a s h e e t 24/24 tsz02201-0b2b0h300010-1-2 ? 2012 rohm co., ltd. all rights reserved. 12.jul.2012 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd91411gw 15.revision history date revision changes 13.jul.2012 001 new release
datasheet d a t a s h e e t notice - rev.003 ? 2012 rohm co., ltd. all rights reserved. notice general precaution 1) before you use our products, you are requested to care fully read this document and fully understand its contents. rohm shall not be in any way responsible or liable for fa ilure, malfunction or accident arising from the use of any rohm?s products against warning, caution or note contained in this document. 2) all information contained in this document is current as of the issuing date and subjec t to change without any prior notice. before purchasing or using rohm?s products, please confirm the la test information with a rohm sales representative. precaution on using rohm products 1) our products are designed and manufactured for applicat ion in ordinary electronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electroni c appliances, amusement equipment, etc.). if you intend to use our products in devices requiring extremel y high reliability (such as medical equipment, transport equipment, traffic equipment, aircraft/spacecra ft, nuclear power controllers, fuel c ontrollers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (?specific applications?), please consult with the rohm sale s representative in advance. unless otherwise agreed in writing by rohm in advance, ro hm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ro hm?s products for specific applications. 2) rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3) our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditio ns, as exemplified below. accordin gly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of an y rohm?s products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified bel ow), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4) the products are not subjec t to radiation-proof design. 5) please verify and confirm characteristics of the final or mounted products in using the products. 6) in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse) is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7) de-rate power dissipation (pd) depending on ambient temper ature (ta). when used in seal ed area, confirm the actual ambient temperature. 8) confirm that operation temperature is within t he specified range described in the product specification. 9) rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document.
datasheet d a t a s h e e t notice - rev.003 ? 2012 rohm co., ltd. all rights reserved. precaution for mounting / circuit board design 1) when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2) in principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification precautions regarding application examples and external circuits 1) if change is made to the constant of an external circuit, pl ease allow a sufficient margin c onsidering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2) you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own indepen dent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1) product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2) even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3) store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4) use products within the specified time after opening a hum idity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohm?s internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since our products might fall under cont rolled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with rohm representative in case of export. precaution regarding intellectual property rights 1) all information and data including but not limited to application example contain ed in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. rohm shall not be in any way responsible or liable for infringement of any intellectual property rights or ot her damages arising from use of such information or data.: 2) no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the information contained in this document.
datasheet d a t a s h e e t notice - rev.003 ? 2012 rohm co., ltd. all rights reserved. other precaution 1) the information contained in this document is provi ded on an ?as is? basis and rohm does not warrant that all information contained in this document is accurate and/or error-free. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or concerning such information. 2) this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 3) the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 4) in no event shall you use in any way whatsoever the pr oducts and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 5) the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties.

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